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integrated silicon solution, inc. 1 rev.b 10/22/2011 copyright ? 2011 integrated silicon solution, inc. all rights reserved. issi reserves the right to make changes to this specifcation and its products at any time without notice. issi assumes no liability arising out of the application or use of any information, products or services described herein. customers are advised to obtain the lat - est version of this device specifcation before relying on any published information and before placing orders for products. integrated silicon solution, inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reason - ably be expected to cause failure of the life support system or to signifcantly affect its safety or effectiveness. products are not authorized for use in such applications unless integrated silicon solution, inc. receives written assurance to its satisfaction, that: a.) the risk of injury or damage has been minimized; b.) the user assume all such risks; and c.) potential liability of integrated silicon solution, inc is adequately protected under the circumstances IS43R16400B features ? vdd and vddq: 2.5v 0.2v (-5, -6) ? vdd and vddq: 2.6v 0.1v (-4) ? sstl_2 compatible i/o ? double-data rate architecture; two data transfers per clock cycle ? bidirectional, data strobe (dqs) is transmitted/ received with data, to be used in capturing data at the receiver ? dqs is edge-aligned with data for reads and centre-aligned with data for writes ? differential clock inputs (ck and ck ) ? dll aligns dq and dqs transitions with ck transitions ? commands entered on each positive ck edge; data and data mask referenced to both edges of dqs ? four internal banks for concurrent operation ? data mask for write data. dm masks write data at both rising and falling edges of data strobe ? burst length: 2, 4 and 8 ? burst type: sequential and interleave mode ? programmable cas latency: 2, 2.5, 3 and 4 ? auto refresh and self refresh modes ? auto precharge ? tras lockout supported (trap = trcd) options ? confguration(s): 4m x16 ? package: 66-pin tsop-ii ? lead-free package available ? temperature range: commercial (0c to +70c) industrial (-40c to +85c) 4mx16 64mb ddr sdram october 2012 device overview issis 64-mbit ddr sdram achieves high speed data transfer using pipeline architecture and two data word accesses per clock cycle. the 67,108,864-bit memory array is internally organized as four banks of 16mb to allow concurrent operations. the pipeline allows read and write burst accesses to be virtually continuous, with the option to concatenate or truncate the bursts. the programmable features of burst length, burst sequence and cas latency enable further advantages. the device is available in 16-bit data word size input data is registered on the i/o pins on both edges of data strobe signal(s), while output data is referenced to both edges of data strobe and both edges of clk. commands are registered on the positive edges of clk. an auto refresh mode is provided, along with a self refresh mode. all i/os are sstl_2 compatible. key timing parameters speed grade -4 -5 -6 units f ck max cl = 4 250 mhz f ck max cl = 3 200 200 166 mhz f ck max cl = 2.5 166 166 mhz f ck max cl = 2 133 133 mhz address table parameter 4m x 16 confguration 1m x 16 x 4 banks bank address pins ba0, ba1 autoprecharge pins a10/ap row addresses a0 C a11 column address a0 C a7 refresh count 4k / 64ms
2 integrated silicon solution, inc. rev.b 10/22/2011 IS43R16400B functional block diagram (4mx16) clk clk cke cs ras cas we a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 ba0 ba1 a11 command decoder & clock genera to r mode register and extended mode register refresh contr oller refresh counter self refresh contro ller ro w address la tch mul tiplexer column address la tch burst counter column address buffer column decoder da ta in buffer da ta out buffer i/o 0-15 v dd /v ddq v ss /v ss q 14 14 12 9 12 12 2 12 9 16 16 16 16 512 (x16) 4096 4096 4096 ro w decoder 4096 memor y cell arra y ba nk 0 sense amp i/o ga te bank contr ol logic ro w address buffer a10 2 ldm, udm udqs , ldqs 2
integrated silicon solution, inc. 3 rev.b 10/22/2011 IS43R16400B pin configurations 66 pin tsop - type ii for x16 v dd dq0 v dd q dq1 dq2 v ss q dq3 dq4 v dd q dq5 dq6 v ss q dq7 nc v ddq ldqs nc vdd nc ldm we cas ras cs nc ba0 ba1 a10/ap a0 a1 a2 a3 vdd 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 v ss dq15 v ss q dq14 dq13 v dd q dq12 dq11 v ss q dq10 dq9 v dd q dq8 nc v ssq udqs nc vref vss udm ck ck cke nc nc a11 a9 a8 a7 a6 a5 a4 vss pin description: a0-a11 row address input a0-a7 column address input ba0, ba1 bank select address dq0 C dq15 data i/o ck, system clock input cke clock enable chip select cas column address strobe command as row address strobe command w write enable ldm, udm data write mask ldqs, udqs data strobe vdd power vddq power supply for i/o pins vss ground vssq ground for i/o pins vref sstl_2 reference voltage nc no connection
4 integrated silicon solution, inc. rev.b 10/22/2011 IS43R16400B pin functional descriptions symbol type description ck, ck input clock: ck and ck are differential clock inputs. all address and control input signals are sampled on the crossing of the positive edge of ck and negative edge of ck. input and output data is referenced to the crossing of ck and ck (both directions of crossing). internal clock signals are derived from ck/ ck . cke input clock enable: cke high activates, and cke low deactivates internal clock signals, and device input buffers and output drivers. taking cke low provides precharge power- down and self refresh operation (all banks idle), or active powerdown (row active in any bank). cke is synchronous for all functions except for self refresh exit, which is achieved asynchronously. input buffers, excluding ck, ck and cke, are disabled during power-down and self refresh mode which are contrived for low standby power consumption. cs input chip select: cs enables (registered low) and disables (registered high) the command decoder. all commands are masked when cs is registered high. cs provides for external bank selection on systems with multiple banks. cs is considered part of the command code. ras , cas , we input we input command inputs: ras , cas and we (along with cs ) defne the command being entered. dm: ldm, udm input input data mask: dm is an input mask signal for write data. input data is masked when dm is sampled high along with that input data during a write access. dm is sampled on both edges of dqs. although dm pins are input-only, the dm loading matches the dq and dqs loading. ldm corresponds to the data on dq0-dq7, udm corresponds to the data on dq8-dq15. ba0, ba1 input input bank address inputs: ba0 and ba1 defne to which bank an active, read, write or precharge command is being applied. a [11:0] input address inputs: provide the row address for active commands, and the column address and auto precharge bit for read / write commands, to select one location out of the memory array in the respective bank. the address inputs also provide the opcode during a mode register set command. dq: dq0-dq15 i/o data bus: input / output dqs: ldqs,udds i/o data strobe: output with read data, input with write data. edge-aligned with read data, centered with write data. used to capture write data. ldqs corresponds to the data on dq0-dq7, udqs corresponds to the data on dq8-dq15. nc -- no connect: should be left unconnected. vref supply sstl_2 reference voltage vddq supply i/o power supply vssq supply i/o ground vdd supply power supply vss supply ground
integrated silicon solution, inc. 5 rev.b 10/22/2011 IS43R16400B simplified state diagram preall = precharge all banks ckel = enter power down mrs = mode register set ckeh = exit power down emrs = extended mode register set act = active se lf au to idl e mr s em rs ro w pr ec har ge wr it e wr it e wr it e read read po we r ac t read a read re fs re fs x re fa c kel mr s c keh c keh c kel wr it e po we r ap p lie d automati cs equenc e command sequenc e read a wr it ea read pr e pr e pr e pr e refr es h refr es h ac ti ve ac ti ve po we r down pr ec har ge po we r down on a read a read a wr it ea bu rs ts to p pr eal l pr ec har ge pr eal l refs = enter self refresh write a = write with autoprecharge refsx = exit self refresh read a = read with autoprecharge refa = auto refresh pre = precharge
6 integrated silicon solution, inc. rev.b 10/22/2011 IS43R16400B functional description the ddr sdram is a high speed cmos, dynamic random-access memory internally confgured as a quad-bank dram. the 64mb devices contains: 67,108,864 bits. the ddr sdram uses double data rate architecture to achieve high speed operation. the double data rate architecture is essentially a 2n prefetch architecture with an interface designed to transfer two data words per clock cycle at the i/o pins. a single read or write access for the ddr sdram effectively consists of a single 2n-bit wide, one clock cycle data transfer at the internal dram core and two corresponding n-bit wide, one-half-clock-cycle data transfers at the i/o pins. read and write accesses to the ddr sdram are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. accesses begin with the registration of an active command, which is then followed by a read or write command. the address bits registered coincident with the active command are used to select the bank and the row to be accessed. the address bits registered coincident with the read or write command are used to select the bank and the starting column location for the burst access. prior to normal operation, the ddr sdram must be initialized. the following section provides detailed information covering device initialization, register defnition, command description and device operation initialization ddr sdrams must be powered up and initialized in a predefned manner. operations procedures other than those specifed may result in undefned operation. if there is any interruption to the device power, the initialization routine should be followed. the steps to be followed for device initialization are listed below. the initialization flow diagram and the initialization flow sequence are shown in the following fgures. the mode register and extended mode register do not have default values. if they are not programmed during the initialization sequence, it may lead to unspecifed operation. the clock stop feature is not available until the device has been properly initialized from step 1 through 13. ? step1: apply vdd before or at the same time as vddq ? step 2: cke must maintain lvcmos low until vref is stable. apply vddq before applying vtt and vref ? step 3: there must be at least 200 s of valid clocks before any command may be given to the dram. during this time nop or deselect commands must be issued on the command bus and cke should be brought high. ? step 4: issue a precharge all command. ? step 5: provide nops or deselect commands for at least trp time. ? step 6: issue emrs command ? step 7: issue mrs command, load the base mode register and to reset the dll. set the desired operating modes. ? step 8: provide nops or deselect commands for at least tmrd time. ? step 9: issue a precharge all command ? step 10: issue 2 or more auto refresh cycles ? step 11: issue mrs command with the reset dll bit deactivated to program operating parameters without resetting the dll ? step 12: provide nop or deselect commands for at least tmrd time. ? step 13: the dram has been properly initialized and is ready for any valid command.
integrated silicon solution, inc. 7 rev.b 10/22/2011 IS43R16400B initialization waveform sequence notes: * = vtt is not applied directly to the device, however tvtd must be greater than or equal to zero to avoid device latch--up. ** = tmrd is required before any command can be applied, and 200 cycles of ck are required before any executable command can be applied the two auto refresh commands may be moved to follow the frst mrs but precede the second precharge all command.
8 integrated silicon solution, inc. rev.b 10/22/2011 IS43R16400B mode register (mr) definition the mode register is used to defne the specifc mode of operation of the ddr sdram. this defnition includes the defnition of a burst length, a burst type, and a cas latency. the mode register is programmed via the mode register set command (with ba0=0 and ba1=0) and will retain the stored information until it is reprogrammed, the device goes into deep power-down mode, or the device loses power. mode register bits a0-a2 specify the burst length, a3 the type of burst (sequential or interleave), a4-a6 the cas latency, and a8 dll reset. a logic 0 should be programmed to all the undefned addresses bits to ensure future compatibility. the mode register must be loaded when all banks are idle and no bursts are in progress, and the controller must wait the specifed time tmrd before initiating any subsequent operation. violating either of these requirements will result in unspecifed operation. reserved states should not be used, as unknown operation or incompatibility with future versions may result mode register ba1 ba0 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 a2 a1 a0 burst length 0 0 0 reserved 0 0 1 2 0 1 0 4 0 1 1 8 1 0 0 reserved 1 0 1 reserved 1 1 0 reserved 1 1 1 reserved address bus (ax) mode reg. (ex) a3 burst type 0 sequential 1 interleave a6 a5 a4 cas latency 0 0 0 reserved 0 0 1 reserved 0 1 0 2 0 1 1 3 1 0 0 4 1 0 1 reserved 1 1 0 2.5 1 1 1 reserved notes: 1. an = most signifcant address bit for this device. 2. a logic 0 should be programmed to all unused / undefned address bits to ensure future compatibility. ba1 ba0 mode register defnition 0 0 program mode register 0 1 program extended mode register 1 0 reserved 1 1 reserved a11 a10 a9 a8 a7 dll 0 0 0 0 0 normal operation 0 0 0 1 0 reset dll
integrated silicon solution, inc. 9 rev.b 10/22/2011 IS43R16400B a2 a1 a0 burst length 0 0 0 reserved 0 0 1 2 0 1 0 4 0 1 1 8 1 0 0 reserved 1 0 1 reserved 1 1 0 reserved 1 1 1 reserved burst length read and write accesses to the ddr sdram are burst oriented, with the burst length being set and the burst order as in burst defnition. the burst length determines the maximum number of column locations that can be accessed for a given read or write command. burst lengths of 2, 4, or 8 locations are available for both the sequential and the interleaved burst types. notes: 1. for a burst length of two, a1-a7 selects the two data element block; a0 selects the frst access within the block. 2. for a burst length of four, a2-a7 selects the four data element block; a0-a1 selects the frst access within the block. 3. for a burst length of eight, a3-a7 selects the eight data element block; a0-a2 selects the frst access within the block. burst definition burst starting column order of accesses within a burst length address type = sequential type = interleaved a0 2 0 0-1 0-1 1 1-0 1-0 a1 a0 0 0 0-1-2-3 0-1-2-3 4 0 1 1-2-3-0 1-0-3-2 1 0 2-3-0-1 2-3-0-1 1 1 3-0-1-2 3-2-1-0 a2 a1 a0 0 0 0 0-1-2-3-4-5-6-7 0-1-2-3-4-5-6-7 0 0 1 1-2-3-4-5-6-7-0 1-0-3-2-5-4-7-6 0 1 0 2-3-4-5-6-7-0-1 2-3-0-1-6-7-4-5 8 0 1 1 3-4-5-6-7-0-1-2 3-2-1-0-7-6-5-4 1 0 0 4-5-6-7-0-1-2-3 4-5-6-7-0-1-2-3 1 0 1 5-6-7-0-1-2-3-4 5-4-7-6-1-0-3-2 1 1 0 6-7-0-1-2-3-4-5 6-7-4-5-2-3-0-1 1 1 1 7-0-1-2-3-4-5-6 7-6-5-4-3-2-1-0
10 integrated silicon solution, inc. rev.b 10/22/2011 IS43R16400B when a read or write command is issued, a block of columns equal to the burst length is effectively selected. all accesses for that burst take place within the block, meaning that the burst will wrap within the block if a boundary is reached. the block is uniquely selected by a1-a7 when the burst length is set to two, by a2-a7 when the burst length is set to 4 and by a3-a7 when the burst length is set to 8. the remaining (least signifcant) address bit(s) is (are) used to select the starting location within the block. the programmed burst length applies to both read and write bursts. burst type accesses within a given burst may be programmed to be either sequential or interleaved; this is referred to as the burst type and is selected via bit a3. the ordering of accesses within a burst is determined by the burst length, the burst type and the starting column address. read latency the read latency, or cas latency, is the delay between the registration of a read command and the availability of the frst piece of output data. if a read command is registered at a clock edge n and the latency is 3 clocks, the frst data element will be valid at n + 2tck + tac. if a read command is registered at a clock edge n and the latency is 2 clocks, the frst data element will be valid at n + tck + tac. operating mode the normal operating mode is selected by issuing a mode register set command with bits a7--a11 each set to zero, and bits a0--a6 set to the desired values. a dll reset is initiated by issuing a mode register set command with bits a7 and a9-- a11 each set to zero, bit a8 set to one, and bits a0--a6 set to the desired values. a mode register set command issued to reset the dll must always be followed by a mode register set command to select normal operating mode (i.e., with a8=0). all other combinations of values for a7-- a11 are reserved for future use and/or test modes. test modes and reserved states should not be used because unknown operation or incompatibility with future versions may result.
integrated silicon solution, inc. 11 rev.b 10/22/2011 IS43R16400B cas latencies
12 integrated silicon solution, inc. rev.b 10/22/2011 IS43R16400B extended mode register (emr) definition the extended mode register controls functions beyond those controlled by the mode register; these additional functions include dll enable/disable, and output drive strength selection. the extended mode register is programmed via the mode register set command (with ba1=0 and ba0=1) and will retain the stored information until it is reprogrammed, or the device loses power. the extended mode register must be loaded when all banks are idle and no bursts are in progress, and the controller must wait the specifed time tmrd before initiating any subsequent operation. violating either of these requirements will result in unspecifed operation. reserved states should not be used, as unknown operation or incompatibility with future versions may result. dll enable/disable the dll must be enabled for normal operation. dll enable is required during power--up initialization, and upon returning to normal operation after having disabled the dll for the purpose of debug or evaluation (upon exiting self refresh mode, the dll is enabled automatically). any time the dll is enabled a dll reset must follow and 200 clock cycles must occur before any executable command can be issued. output driver strength (ds) the normal drive strength for all outputs is specifed to be sstl_2, class ii. this dram also supports a weak driver strength option, intended for lighter load and/or point--to--point environments. i--v curves for the normal drive strength and weak drive strength are included in this datasheet. extended mode register definition ba1 ba0 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 a0 dll 0 enable 1 disable address bus (ax) ext. mode reg. (ex) extended mode register a6 a1 drive strength 0 0 full (100%) 0 1 weak (60%) 1 0 reserved 1 1 matched (30%) notes: 1. msb depends on ddr sdram density. 2. a logic 0 should be programmed to all unused/undefned ad - dress bits to ensure future compatibility ba1 ba0 mode register defnition 0 0 program mode register 0 1 program extended mode register 1 0 reserved 1 1 reserved reserved (2) reserved (2)
integrated silicon solution, inc. 13 rev.b 10/22/2011 IS43R16400B absolute maximum rating parameter symbol value unit voltage on any pin relative to vss v in , v out -1.0 ~ 3.6 v voltage on vdd & vddq supply relative to vss v dd , v ddq -1.0 ~ 3.6 v storage temperature t stg -55 ~ +150 o c power dissipation p d 1 w short circuit current i os 50 ma note: 1. permanent device damage may occur if absolute maximum ratings are exceeded. 2. functional operation should be restricted to recommend operation condition. 3. exposure to higher than recommended voltage for extended periods of time could affect device reliability ac/dc electrical characteristics and operating conditions recommended operating conditions (voltage referenced to vss=0v, ta=0 to 70 o c for commercial. ta = -40 o c to +85 o c for industrial) parameter symbol min max unit note supply voltage (for device with a nominal vdd of 2.5v for -5, -6) v dd 2.3 2.7 v supply voltage (for device with a nominal vdd of 2.6v for -4) v dd 2.5 2.7 v i/o supply voltage (for device with a nominal vdd of 2.5v for -5, -6) v ddq 2.3 2.7 v i/o supply voltage (for device with a nominal vdd of 2.6v for -4) v ddq 2.5 2.7 v i/o reference voltage v ref 0.49*vddq 0.51*vddq v 1 i/o termination voltage (system) v tt vref-0.04 vref+0.04 v 2 input logic high voltage v ih ( dc ) vref+0.15 vddq+0.3 v input logic low voltage v il ( dc ) -0.3 vref-0.15 v input voltage level, clk and clk inputs v in ( dc ) -0.3 vddq+0.3 v input differential voltage, clk and clk inputs v id ( dc ) 0.36 vddq+0.6 v 3 v-i matching: pullup to pulldown current ratio v i (ratio) 0.71 1.4 C 4 input leakage current i l -2 2 ua output leakage current i oz -5 5 ua output high current (full strength driver) ; vout = vtt + 0.84v i oh -16.8 C ma output low current (full strength driver) ; vout = vtt - 0.84v i ol 16.8 C ma output high current (weak strength driver); vout = vtt + 0.45v i ohr -9 C ma output low current (weak strength driver); vout = vtt - 0.45v i olr 9 C ma ambient operating temperature commercial industrial t a t a 0 -40 +70 +85 o c o c note : 1. vref is expected to be equal to 0.5*vddq of the transmitting device, and to track variations in the dc level of same. peak-to peak noise on vref may not exceed +/-2% of the dc value. 2. vtt is not applied directly to the device. vtt is a system supply for signal termination resistors, is expected to be set equal to vref, and must track variations in the dc level of vref 3. vid is the magnitude of the difference between the input level on clk and the input level on clk. 4. the ratio of the pullup current to the pulldown current is specifed for the same temperature and voltage, over the entire tem - perature and voltage range, for device drain to source voltages from 0.25v to 1.0v. for a given output, it represents the maxi - mum difference between pullup and pulldown drivers due to process variation. the full variation in the ratio of the maximum to minimum pullup and pulldown current will not exceed 1.7 for device drain to source voltages from 0.1 to 1.0.
14 integrated silicon solution, inc. rev.b 10/22/2011 IS43R16400B capacitance characteristics (1,2) (v dd = v ddq = 2.5v 0.2v (-5, -6), v dd = v ddq = 2.6v 0.1v (-4), unless otherwise noted) symbol parameter limits units min max ci(a) input capacitance, address pin 1.3 3 pf ci(c) input capacitance, control pin 1.3 3 pf ci(k) input capacitance, clk pin 1.3 3 pf ci/o i/o capacitance, i/o, dqs, dm pin 3 5 pf note : 1. this parameter is characterized. 2. conditions: frequency = 100mhz; v out (dc) = v dd /2; v out (peak-to-peak) = 0.2v; v ref = vss package substrate theta-ja (airfow = 0m/s) theta-ja (airfow = 1m/s) theta-ja (airfow = 2m/s) theta-jc units tsop2(66) 4-layer 113.3 102.1 96.7 26.1 c/w thermal resistance
integrated silicon solution, inc. 15 rev.b 10/22/2011 IS43R16400B idd specifcation parameters and test conditions: x16 (v dd = v ddq = 2.5v + 0.2v (-6, -75), v dd = v ddq = 2.6v + 0.1v (-4, -5), vss = vss q = 0v, output open, unless otherwise noted) symbol parameter/ test condition -4 -5 -6 units idd0 operating current for one bank active-precharge; trc = trc(min); tck = tck(min); dq, dm and dqs inputs changing once per clock cycle; address and control inputs changing once every two clock cycles; cs = high between valid commands 85 75 65 ma idd1 operating current for one bank operation; one bank open; bl = 4; trc = trc(min); tck = tck(min); iout=0ma; address and control inputs changing once per clock cycle; 50% of data changing on every transfer 120 95 85 ma idd2p precharge power-down standby current; all banks idle; power-down mode; cke vil(max); tck = tck(min); vin = vref for dq, dqs and dm 4 4 4 ma idd2n precharge foating standby current; cs vih(min); all banks idle; cke vih(min); tck = tck(min); address and other control inputs changing once per clock cycle; vin = vref for dq, dqs and dm 75 65 55 ma idd3p active power-down standby current; one bank active; power-down mode; cke vil(max); tck = tck(min); vin = vref for dq, dqs and dm 35 28 22 ma idd3n active standby current; cs vih(min); cke vih(min); one bank active; trc = tras(max); tck = tck(min); dq, dqs and dm inputs changing twice per clock cycle; address and other control inputs changing once per clock cycle 80 70 60 ma idd4r operating current for burst read; burst length = 2; reads; continuous burst; one bank active; address and control inputs changing once per clock cycle; tck = tck(min); 50% of data changing on every transfer; lout = 0ma 180 160 140 ma idd4w operating current for burst write; burst length = 2; writes; continuous burst; one bank active address and control inputs changing once per clock cycle; tck = tck(min); dq, dm and dqs inputs changing twice per clock cycle, 50% of input data changing at every transfer 190 165 145 ma idd5 auto refresh current; trc = trfc(min) 100 95 90 ma idd6 self refresh current; cke 0.2v 3 3 3 ma idd7 operating current for four bank operation; four bank interleaving reads (bl=4) with auto precharge; trc = trc(min), tck = tck(min); address and control inputs change only during active, read, or write commands; 50% of data changing on every transfer 200 180 160 ma
16 integrated silicon solution, inc. rev.b 10/22/2011 IS43R16400B parameter symbol -4 -5 units min max min max dq output access time for clk,/clk tac -0.7 0.7 -0.7 0.7 ns dqs output access time for clk,/clk tdqsck -0.6 0.6 -0.6 0.6 ns clk high-level width tch 0.45 0.55 0.45 0.55 tck clk low-level width tcl 0.45 0.55 0.45 0.55 tck clk half period thp min (tcl,tch) C min (tcl,tch) C ns clk cycle time cl=4 tck(4) 4 10 C C ns cl=3 tck(3) 5 10 5 10 ns cl=2.5 tck(2.5) C C 6 10 ns cl=2 tck(2) C C 7.5 10 ns dq and dm input hold time tdh 0.4 C 0.4 C ns dq and dm input setup time tds 0.4 C 0.4 C ns control & address input pulse width (for each input) tipw 2.2 C 2.2 C ns dq and dm input pulse width (for each input) tdipw 1.75 C 1.75 C ns dq & dqs high-impedance time from clk,/clk thz C 0.7 C 0.7 ns dq & dqs low--impedance time from clk,/clk tlz -0.7 C -0.7 C ns dqs--dq skew, dqs to last dq valid, per group, per access tdqsq C 0.4 C 0.4 ns dq/dqs output hold time from dqs tqh thp-tqhs C thp-tqhs C ns data hold skew factor tqhs C 0.5 C 0.5 ns write command to frst dqs latching transition tdqss 0.72 1.28 0.72 1.28 tck dqs input high pulse width tdqsh 0.35 C 0.35 C tck dqs input low pulse width tdqsl 0.35 C 0.35 C tck dqs falling edge to clk setup time tdss 0.2 C 0.2 C tck dqs falling edge hold time from clk tdsh 0.2 C 0.2 C tck mode register set command cycle time tmrd 2 C 2 C tck write preamble setup time twpres 0 C 0 C ns write postamble twpst 0.4 0.6 0.4 0.6 tck write preamble twpre 0.25 C 0.25 C tck address and control input hold time (fast slew rate) tihf 0.6 C 0.6 C ns address and control input setup time (fast slew rate) tisf 0.6 C 0.6 C ns address and control input hold time (slow slew rate) tih 0.7 -C 0.7 C ns address and control input setup time (slow slew rate) tis 0.7 C 0.7 C ns read preamble trpre 0.9 1.1 0.9 1.1 tck read postamble trpst 0.4 0.6 0.4 0.6 tck active to precharge command tras 40 70,000 40 70,000 ns ac timing requirements absolute specifcations (vdd, vddq = 2.6v 0.1v (-4), 2.5v 0.2v (-5, -6)
integrated silicon solution, inc. 17 rev.b 10/22/2011 IS43R16400B parameter symbol -4 -5 units min max min max active to active/auto refresh command period trc 55 C 55 C ns auto refresh to active/auto trfc 60 C 70 C ns active to read or write delay trcd 16 C 15 C ns precharge command period trp 16 C 15 C ns active to autoprecharge delay trap 15 C 15 C ns active bank a to active bank b command trrd 10 C 10 C ns write recovery time twr 12 C 15 C ns auto precharge write recovery + precharge time tdal twr+trp C twr+trp C tck internal write to read command delay twtr 2 C 2 C tck exit self refresh to non-read txsnr 75 C 75 C ns exit self refresh to read command txsrd 200 C 200 C tck average periodic refresh interval trefi C 15.6 C 15.6 m s ac timing requirements absolute specifcations (vdd, vddq = 2.6v 0.1v (-4), 2.5v 0.2v (-5, -6)
18 integrated silicon solution, inc. rev.b 10/22/2011 IS43R16400B parameter symbol -6 units min max dq output access time for clk,/clk tac -0.7 0.7 ns dqs output access time for clk,/clk tdqsck -0.6 0.6 ns clk high-level width tch 0.45 0.55 tck clk low-level width tcl 0.45 0.55 tck clk half period thp min (tcl,tch) C ns clk cycle time cl=4 tck(4) C C ns cl=3 tck(3) 6 12 ns cl=2.5 tck(2.5) 6 12 ns cl=2 tck(2) 7.5 12 ns dq and dm input hold time tdh 0.45 C ns dq and dm input setup time tds 0.45 C ns control & address input pulse width (for each input) tipw 2.2 C ns dq and dm input pulse width (for each input) tdipw 1.75 C ns dq & dqs high-impedance time from clk,/clk thz C 0.7 ns dq & dqs low--impedance time from clk,/clk tlz -0.7 C ns dqs--dq skew, dqs to last dq valid, per group, per access tdqsq C 0.45 ns dq/dqs output hold time from dqs tqh thp-tqhs C ns data hold skew factor tqhs C 0.55 ns write command to frst dqs latching transition tdqss 0.75 1.25 tck dqs input high pulse width tdqsh 0.35 C tck dqs input low pulse width tdqsl 0.35 C tck dqs falling edge to clk setup time tdss 0.2 C tck dqs falling edge hold time from clk tdsh 0.2 C tck mode register set command cycle time tmrd 2 C tck write preamble setup time twpres 0 C ns write postamble twpst 0.4 0.6 tck write preamble twpre 0.25 C tck address and control input hold time (fast slew rate) tihf 0.75 C ns address and control input setup time (fast slew rate) tisf 0.75 C ns address and control input hold time (slow slew rate) tih 0.8 -C ns address and control input setup time (slow slew rate) tis 0.8 C ns read preamble trpre 0.9 1.1 tck read postamble trpst 0.4 0.6 tck active to precharge command tras 42 120,000 ns ac timing requirements absolute specifcations (vdd, vddq = 2.6 v 0.1v (-4), 2.5v 0.2v (-5, -6)
integrated silicon solution, inc. 19 rev.b 10/22/2011 IS43R16400B parameter symbol -6 units min max active to active/auto refresh command period trc 60 C ns auto refresh to active/auto trfc 70 C ns active to read or write delay trcd 18 C ns precharge command period trp 18 C ns active to autoprecharge delay trap 18 C ns active bank a to active bank b command trrd 12 C ns write recovery time twr 15 C ns auto precharge write recovery + precharge time tdal twr+trp C tck internal write to read command delay twtr 1 C tck exit self refresh to non-read txsnr 75 C ns exit self refresh to read command txsrd 200 C tck average periodic refresh interval trefi C 15.6 m s ac timing requirements absolute specifcations (vdd, vddq = 2.6 v 0.1v (-4), 2.5v 0.2v (-5, -6)
20 integrated silicon solution, inc. rev.b 10/22/2011 IS43R16400B output load condition dq output ti mi ng measurement re fe re n ce po in t v re f v re f dqs v out v re f 30 pf 50 v tt =v re f zo =5 0 ? ?
integrated silicon solution, inc. 21 rev.b 10/22/2011 IS43R16400B notes 1. all voltages referenced to vss. 2. tests for ac timing, idd, and electrical, ac and dc characteristics, may be conducted at nominal reference/supply voltage levels, but the related specifcations and device operation are guaranteed for the full voltage range specifed. 3. ac timing and idd tests may use a vil to vih swing of up to 1.5v in the test environment, but input timing is still referenced to vref (or to the crossing point for ck//ck), and parameter specifcations are guaranteed for the specifed ac input levels un - der normal use conditions. the minimum slew rate for the input signals is 1v/ns in the range between vil(ac) and vih(ac). 4. the ac and dc input level specifcations are as defned in the sstl_2 standard (i.e. the receiver will effectively switch as a result of the signal crossing the ac input level, and will remain in that state as long as the signal does not ring back above (below) the dc input low (high) level. 5. vref is expected to be equal to 0.5*vddq of the transmitting device, and to track variations in the dc level of the same. peak-to-peak noise on vref may not exceed +2% of the dc value. 6. vtt is not applied directly to the device. vtt is a system supply for signal termination resistors, is expected to be set equal to vref, and must track variations in the dc level of vref. 7. vid is the magnitude of the difference between the input level on clk and the input level on /clk. 8. the value of vix is expected to equal 0.5*vddq of the transmitting device and must track variations in the dc level of the same. 9. enables on-chip refresh and address counters. 10. idd specifcations are tested after the device is properly initialized. 11. this parameter is sampled. vddq = 2.5v+0.2v, vdd = 2.5v + 0.2v , f = 100 mhz, ta = 25 o c, vout(dc) = vddq/2, vout(peak to peak) = 25mv. dm inputs are grouped with i/o pins - refecting the fact that they are matched in loading (to facilitate trace matching at the board level). 12. the clk//clk input reference level (for timing referenced to clk//clk) is the point at which clk and /clk cross; the input reference level for signals other than clk//clk, is vref. 13. inputs are not recognized as valid until vref stabilizes. exception: during the period before vref stabilizes, cke< 0.3vddq is recognized as low. 14. thz and tlz transitions occur in the same access time windows as valid data transitions. these parameters are not refer - enced to a specifc voltage level, but specify when the device output is no longer driving (hz), or begins driving (lz). 15. the maximum limit for this parameter is not a device limit. the device will operate with a greater value for this parameter, but system performance (bus turnaround) will degrade accordingly. 16. the specifc requirement is that dqs be valid (high, low, or at some point on a valid transition) on or before this clk edge. a valid transition is defned as monotonic, and meeting the input slew rate specifcations of the device. when no writes were previously in progress on the bus, dqs will be transitioning from high-z to logic low. if a previous write was in prog - ress, dqs could be high, low, or transitioning from high to low at this time, depending on tdqss. 17. a maximum of eight auto refresh commands can be posted to any given ddr sdram device. 18. txprd should be 200 tclk in the condition of the unstable clk operation during the power down mode. 19. for command/address and ck & /ck slew rate > 1.0v/ns. 20. min (tcl,tch) refers to the smaller of the actual clock low time and the actual clock high time as provided to the device.
22 integrated silicon solution, inc. rev.b 10/22/2011 IS43R16400B output slew rate characteristics slew rate characteristic typical range (v/ns) min (v/ns) max (v/ns) pullup slew rate 1.2-2.5 0.7 5.0 pulldown slew rate 1.2-2.5 0.7 5.0 ac overshoot/undershoot specification for address and control pins parameter max units peak amplitude allowed for overshoot 1.5 v peak amplitude allowed for undershoot 1.5 v area between the overshoot signal and vdd must be less than or equal to (see fgure below) 4.5 v-ns area between the undershoot signal and gnd must be less than or equal to (see fgure below) 4.5 v-ns overshoot/undershoot specification for data, strobe, and mask pins parameter max units peak amplitude allowed for overshoot 1.2 v peak amplitude allowed for undershoot 1.2 v area between the overshoot signal and vdd must be less than or equal to (see fgure below) 2.4 v-ns area between the undershoot signal and gnd must be less than or equal to (see fgure below) 2.4 v-ns address and control ac overshoot and undershoot defnition dq/dm/dqs ac overshoot and undershoot defnition ground v dd -3 -2 -1 +1 +2 +3 +4 +5 0 01 23 456 ti me (ns ) vo lt s (v ) undershoot overshoo t max .a m plitude =1 .5 v max. ar ea =4 .5 v- ns v dd -3 -2 -1 +1 +2 +3 +4 +5 0 01 23 456 vo lt s (v ) undershoot overshoot max. amplitude =1 .2 v ti me (ns) ground max. ar ea =2 .4 v- -n s
integrated silicon solution, inc. 23 rev.b 10/22/2011 IS43R16400B driver characteristics ddr sdram output driver characteristics are defned for full and weak drive strength operation as selected in the extended mode register bits a1 and a6. the table below shows the data in a tabular format suitable for input into simulation tools. the following fgures show the driver strength characteristics graphically. full strength driver characteristics voltage (v) pull down current (ma) pull up current (ma) nominal nominal min. max. nominal nominal min. max. low high low high 0.1 6.0 6.8 4.6 9.6 -6.1 -7.6 -4.6 10.0 0.2 12.2 13.5 9.2 18.2 12.2 14.5 -9.2 20.0 0.3 18.1 20.1 13.8 26.0 18.1 21.2 13.8 29.8 0.4 24.1 26.6 18.4 33.9 24.0 27.7 18.4 38.8 0.5 29.8 33.0 23.0 41.8 29.8 34.1 23.0 46.8 0.6 34.6 39.1 27.7 49.4 34.3 40.5 27.7 54.4 0.7 39.4 44.2 32.2 56.8 38.1 46.9 32.2 61.8 0.8 43.7 49.8 36.8 63.2 41.1 53.1 36.0 69.5 0.9 47.5 55.2 39.6 69.9 43.8 59.4 38.2 77.3 1.0 51.3 60.3 42.6 76.3 46.0 65.5 38.7 85.2 1.1 54.1 65.2 44.8 82.5 47.8 71.6 39.0 93.0 1.2 56.2 69.9 46.2 88.3 49.2 77.6 39.2 100.6 1.3 57.9 74.2 47.1 93.8 50.0 83.6 39.4 108.1 1.4 59.3 78.4 47.4 99.1 50.5 89.7 39.6 115.5 1.5 60.1 82.3 47.7 103.8 50.7 95.5 39.9 123.0 1.6 60.5 85.9 48.0 108.4 51.0 101.3 40.1 130.4 1.7 61.0 89.1 48.4 112.1 51.1 107.1 40.2 136.7 1.8 61.5 92.2 48.9 115.9 51.3 112.4 40.3 144.2 1.9 62.0 95.3 49.1 119.6 51.5 118.7 40.4 150.5 2.0 62.5 97.2 49.4 123.3 51.6 124.0 40.5 156.9 2.1 62.9 99.1 49.6 126.5 51.8 129.3 40.6 163.2 2.2 63.3 100.9 49.8 129.5 52.0 134.6 40.7 169.6 2.3 63.8 101.9 49.9 132.4 52.2 139.9 40.8 176.0 2.4 64.1 102.8 50.0 135.0 52.3 145.2 40.9 181.3 2.5 64.6 103.8 50.2 137.3 52.5 150.5 41.0 187.6 2.6 64.8 104.6 50.4 139.2 52.7 155.3 41.1 192.9 2.7 65.0 105.4 50.5 140.8 52.8 160.1 41.2 198.2 note : the "weak output driver" is 60% of the full strength output driver. the "matched output driver" is 30% of the full strength output driver.
24 integrated silicon solution, inc. rev.b 10/22/2011 IS43R16400B pullup characteristics for full strength output driver -- 250 -- 200 -- 150 -- 100 -- 50 0 0 0. 5 1 1. 5 2 2. 5 3 vddq to vo ut (v ) pullu pc urren t( ma ) nomi nal low nomi nal hi gh minimum max i mum pulldown characteristics for full strength output driver 0 20 40 60 80 100 120 140 160 00 .5 11 .5 22 .5 3 vout to vssq (v) pulldown cu rre nt (ma) nomi nal low nomi nal hi gh minimum max i mum
integrated silicon solution, inc. 25 rev.b 10/22/2011 IS43R16400B commands truth tables all commands (address and control signals) are registered on the positive edge of clock (crossing of ck going high and ck going low). truth table shows basic timing parameters for all commands. truth tables for commands provide a quick reference of available commands. table "current state" provides the current state / next state information. this is followed by a detailed description of each command. truth table - commands name (function) cs ras cas we addr notes deselect (nop) h x x x x 9 no operation (nop) l h h h x 9 active (select bank and activate row) l l h h bank/row 3 read (select bank and column, and start read burst) l h l h bank/col 4 write (select bank and column, and start write burst) l h l l bank/col 4 burst terminate l h h l x 8 precharge (deactivate row in bank or banks) l l h l code 5 auto refresh or self refresh (enter self refresh mode) l l l h x 6, 7, 12 mode register set l l l l op-code 2 truth table - dm operations name (function) dm dqs notes write enable l valid 10 write inhibit h x 10 note: 1. cke is high for all commands shown except self refresh. 2. ba0--ba1 select either the base or the extended mode register (ba0 = 0, ba1 = 0 selects mode register; ba0 = 1, ba1 = 0 selects extended mode register; other combinations of ba0--ba1 are reserved; a0--an provide the op--code to be written to the selected mode register. 3. ba0--ba1 provide bank address and a0--an provide row address. 4. ba0--ba1 provide bank address; a0--ai provide column address; ap high enables the auto precharge feature (nonpersis - tent), ap low disables the auto precharge feature. 5. ap low: ba0--ba1 determine which bank is precharged. ap high: all banks are precharged and ba0--ba1 are dont care. 6. this command is auto refresh if cke is high; self refresh if cke is low. 7. internal refresh counter controls row addressing; all inputs and i/os are dont care except for cke. 8. applies only to read bursts with autoprecharge disabled; this command is undefned (and should not be used) for read bursts with autoprecharge enabled, and for write bursts. 9. deselect and nop are functionally interchangeable. 10. used to mask write data, provided coincident with the corresponding data. 11. operation or timing that is not specifed is illegal and after such an event, in order to guarantee proper operation, the dram must be powered down and then restarted through the specifed initialization sequence before normal operation can continue. 12. vref must be maintained during self refresh operation.
26 integrated silicon solution, inc. rev.b 10/22/2011 IS43R16400B truth table - cke cken-1 cken current state commandn actionn notes l l power-down x maintain power-down l l self refresh x maintain self refresh 7 l h power-down deselect or nop exit power-down l h self refresh deselect or nop exit self refresh 5, 7 h l all banks idle deselect or nop precharge power- down entry h l bank(s) active deselect or nop active power-down entry h l all banks idle auto refresh self refresh entry h h see next truth table note: 1. cken is the logic state of cke at clock edge n; cken--1 was the state of cke at the previous clock edge. 2. current state is the state of the ddr sdram immediately prior to clock edge n. 3. commandn is the command registered at clock edge n, and actionn is a result of commandn. 4. all states and sequences not shown are illegal or reserved. 5. deselect or nop commands should be issued on any clock edges occurring during the txsnr or txsrd period. a mini - mum of 200 clock cycles is needed before applying any executable command, for the dll to lock. 6. operation or timing that is not specifed is illegal and after such an event, in order to guarantee proper operation, the dram must be powered down and then restarted through the specifed initialization sequence before normal operation can continue. 7. vref must be maintained during self refresh operation.
integrated silicon solution, inc. 27 rev.b 10/22/2011 IS43R16400B truth table - current state bank n -- command to bank n current state cs ras cas we command/action notes any h x x x deselect (nop/continue previous operation) l h h h no operation (nop/continue previous operation) idle l l h h active (select and activate row) l l l h auto refresh 7 l l l l mode register set 7 row active l h l h read (select column and start read burst) 10 l h l l write (select column and start write burst) 10 l l h l precharge (deactivate row in bank or banks) 8 read (auto- precharge disabled) l h l h read (select column and start new read burst) 10 l h l l write (select column and start new write burst) 10, 12 l l h l precharge (truncate read burst, start precharge) 8 l h h l burst terminate 9 write (auto- precharge disabled) l h l h read (select column and start read burst) 10, 11 l h l l write (select column and start new write burst) 10 l l h l precharge (truncate write burst, start precharge) 8, 11 note: 1. this table applies when cken--1 was high and cken is high (see truth table 2) and after txsnr or txsrd has been met (if the previous state was self refresh). 2. this table is bank--specifc, except where noted, i.e., the current state is for a specifc bank and the commands shown are those allowed to be issued to that bank when in that state. exceptions are covered in the notes below. 3. current state defnitions: idle: the bank has been precharged, and trp has been met. row active: a row in the bank has been activated, and trcd has been met. no data bursts/accesses and no register ac - cesses are in progress. read: a read burst has been initiated, with auto precharge disabled, and has not yet terminated or been terminated. write: a write burst has been initiated, with auto precharge disabled, and has not yet terminated or been terminated. 4. the following states must not be interrupted by a command issued to the same bank. deselect or nop commands, or allowable commands to the other bank should be issued on any clock edge occurring during these states. allowable com - mands to the other bank are determined by its current state and truth table 3, and according to truth table 4. precharging: starts with registration of a precharge command and ends when trp is met. once trp is met, the bank will be in the idle state. row activating: starts with registration of an active command and ends when trcd is met. once trcd is met, the bank will be in the row active state. read w/auto-precharge enabled: starts with registration of a read command with auto precharge enabled and ends when trp has been met. once trp is met, the bank will be in the idle state. write w/auto-precharge enabled: starts with registration of a write command with auto precharge enabled and ends when trp has been met. once trp is met, the bank will be in the idle state. 5. the following states must not be interrupted by any executable command; deselect or nop commands must be applied on each positive clock edge during these states. refreshing: starts with registration of an auto refresh command and ends when trc is met. once trfc is met, the ddr sdram will be in the all banks idle state. accessing mode register: starts with registration of a mode register set command and ends when tmrd has been met. once tmrd is met, the ddr sdram will be in the all banks idle state. precharging all: starts with registration of a precharge all command and ends when trp is met. once trp is met, all banks will be in the idle state. 6. all states and sequences not shown are illegal or reserved. 7. not bank--specifc; requires that all banks are idle and no bursts are in progress. 8. may or may not be bank--specifc; if multiple banks are to be precharged, each must be in a valid state for precharging. 9. not bank--specifc; burst terminate affects the most recent read burst, regardless of bank. 10. reads or writes listed in the command/action column include reads or writes with auto precharge enabled and reads or writes with auto precharge disabled. 11. requires appropriate dm masking. 12. a write command may be applied after the completion of the read burst; otherwise, a burst terminate must be used to end the read prior to asserting a write command, 13. operation or timing that is not specifed is illegal and after such an event, in order to guarantee proper operation, the dram must be powered down and then restarted through the specifed initialization sequence before normal operation can continue.
28 integrated silicon solution, inc. rev.b 10/22/2011 IS43R16400B truth table - current state bank n - command to bank m current state cs ras cas we command/action notes any h x x x deselect (nop/continue previous operation) l h h h no operation (nop/continue previous operation) idle x x x x any command otherwise allowed to bank m row activating, active, or precharging l l h h active (select and activate row) l h l h read (select column and start read burst) 7 l h l l write (select column and start write burst) 7 l l h l precharge read (auto- precharge disabled) l l h h active (select and activate row) l h l h read (select column and start new read burst) 7 l h l l write (select column and start new write burst) 7, 9 l l h l precharge write (auto- precharge disabled) l l h h active (select and activate row) l h l h read (select column and start read burst) 7, 8 l h l l write (select column and start new write burst) 7 l l h l precharge read (with auto- precharge) l l h h active (select and activate row) l h l h read (select column and start new read burst) 3a, 7 l h l l write (select column and start write burst) 3a, 7, 9 l l h l precharge write (with auto-precharge) l l h h active (select and activate row) l h l h read (select column and start read burst) 3a, 7 l h l l write (select column and start new write burst) 3a, 7 l l h l precharge note: 1. this table applies when cken--1 was high and cken is high and after txsnr or txsrd has been met (if the previous state was self refresh). 2. this table describes alternate bank operation, except where noted, i.e., the current state is for bank n and the commands shown are those allowed to be issued to bank m (assuming that bank m is in such a state that the given command is allow - able). exceptions are covered in the notes below. 3. current state defnitions: idle: the bank has been precharged, and trp has been met. row active: a row in the bank has been activated, and trcd has been met. no data bursts/accesses and no register ac - cesses are in progress. read: a read burst has been initiated, with auto precharge disabled and has not yet terminated or been terminated. write: a write burst has been initiated, with auto precharge disabled and has not yet terminated or been terminated. read with auto-precharge enabled: see following text, notes 3a, 3b, and 3c: write with auto-precharge enabled: see following text, notes 3a, 3b, and 3c: 3a. for devices which do not support the optional concurrent auto precharge feature, the read with auto precharge enabled or write with auto precharge enabled states can each be broken into two parts: the access period and the precharge period. for read with auto precharge, the precharge period is defned as if the same burst was executed with auto precharge dis - abled and then followed with the earliest possible precharge command that still accesses all of the data in the burst. for write with auto precharge, the precharge period begins when twr ends, with twr measured as if auto precharge was dis - abled. the access period starts with registration of the command and ends where the precharge period (or trp) begins.dur - ing the precharge period of the read with auto precharge enabled or write with auto precharge enabled states, active, precharge, read and write commands to the other bank may be applied; during the access period, only active and precharge commands to the other bank may be applied. in either case, all other related limitations apply (e.g., contention between read data and write data must be avoided).
integrated silicon solution, inc. 29 rev.b 10/22/2011 IS43R16400B 3b. for devices which do support the optional concurrent auto precharge feature, a read with auto precharge enabled, or a write with auto precharge enabled, may be followed by any command to the other banks, as long as that command does not interrupt the read or write data transfer, and all other related limitations apply (e.g., contention between read data and write data must be avoided.) 3c. the minimum delay from a read or write command with auto precharge enable, to a command to a different bank, is summa - rized below, for both cases of concurrent auto precharge, supported or not: 4. auto refresh and mode register set commands may only be issued when all banks are idle. 5. a burst terminate command cannot be issued to another bank; it applies to the bank represented by the current state only. 6. all states and sequences not shown are illegal or reserved. 7. reads or writes listed in the command/action column include reads or writes with auto precharge enabled and reads or writes with auto precharge disabled. 8. requires appropriate dm masking. 9. a write command may be applied after the completion of data output, otherwise a burst terminate must be used to the read prior to asserting a write command.. 10. operation or timing that is not specifed is illegal and after such an event, in order to guarantee proper operation, the dram must be powered down and then restarted through the specifed initialization sequence before normal operation can continue.
30 integrated silicon solution, inc. rev.b 10/22/2011 IS43R16400B operation deselect the deselect function ( cs = high) prevents new commands from being executed by the ddr sdram. the ddr sdram is effectively deselected. operations already in progress are not affected. no operation the no operation (nop) command is used to perform a nop to a ddr sdram that is selected ( cs = low). this prevents unwanted commands from being registered during idle or wait states. operations already in progress are not affected. mode register set the mode register and the extended mode register are loaded via the address inputs. see "mode register" and the "extended mode register" descriptions for further details. the mode register set command can only be issued when all banks are idle and no bursts are in progress, and a subsequent executable command cannot be issued until tmrd is met.
integrated silicon solution, inc. 31 rev.b 10/22/2011 IS43R16400B active before any read or write commands can be issued to a bank in the ddr sdram, a row in that bank must be opened. this is accomplished by the active command: ba0 and ba1 select the bank, and the address inputs select the row to be activated. more than one bank can be active at anytime. once a row is open, a read or write command could be issued to that row, subject to the trcd specifcation. a subsequent active command to another row in the same bank can only be issued after the previous row has been closed. the minimum time interval between two successive active commands on the same bank is defned by trc. a subsequent active command to another bank can be issued while the frst bank is being accessed, which results in a reduction of total row access overhead. the minimum time interval between two successive active commands on different banks is defned by trrd. bank activation command cycle shows the trcd and trrd defnition. the row remains active until a precharge command (or read or write command with auto precharge) is issued to the bank. a precharge command (or read or write command with auto precharge) must be issued before opening a different row in the same bank. bank activation command cycle note: all command and timing diagrams are with ap = a10.
32 integrated silicon solution, inc. rev.b 10/22/2011 IS43R16400B read the read command is used to initiate a burst read access to an active row, with a burst length as set in the mode register. ba0 and ba1 select the bank, and the address inputs select the starting column location. the value of a10 determines whether or not auto precharge is used. if auto precharge is selected, the row being accessed will be precharged at the end of the read burst; if auto precharge is not selected, the row will remain open for subsequent accesses. the basic read timing parameters for dqs are shown in figure basic read timing parameters they apply to all read operations. during read bursts, dqs is driven by the ddr sdram along with the output data. the initial low state of the dqs is known as the read preamble; the low state coincident with last data-out element is known as the read postamble. the frst data-out element is edge aligned with the frst rising edge of dqs and the successive data-out elements are edge aligned to successive edges of dqs. this is shown in figure read burst showing cas latency with a cas latency of 2 and 3. upon completion of a read burst, assuming no other read command has been initiated, the dqs will go to high-z. read command
integrated silicon solution, inc. 33 rev.b 10/22/2011 IS43R16400B read to read data from a read burst may be concatenated or truncated by a subsequent read command. the frst data from the new burst follows either the last element of a completed burst or the last desired element of a longer burst that is being truncated. the new read command should be issued x cycles after the frst read command, where x equals the number of desired data-out element pairs (pairs are required by the 2n prefetch architecture). a read command can be initiated on any clock cycle following a previous read command. full-speed random read accesses within a page or pages can be performed as shown in figure random read bursts. read burst terminate data from any read burst may be truncated with a burst terminate command. the burst terminate latency is equal to the read (cas) latency, i.e., the burst terminate command should be issued x cycles after the read command where x equals the desired data-out element pairs. read to write data from read burst must be completed or truncated before a subsequent write command can be issued. if truncation is necessary, the burst terminate command must be used, as shown in figure read to write for the case of nominal tdqss. read to precharge a read burst may be followed by or truncated with a precharge command to the same bank (provided auto precharge was not activated). the precharge command should be issued x cycles after the read command, where x equal the number of desired data-out element pairs. following the precharge command, a subsequent command to the same bank cannot be issued until trp is met. note that part of the row precharge time is hidden during the access of the last data-out elements. in the case of a read being executed to completion, a precharge command issued at the optimum time (as described above) provides the same operation that would result from read burst with auto precharge enabled. the disadvantage of the precharge command is that it requires that the command and address buses be available at the appropriate time to issue the command. the advantage of the precharge command is that it can be used to truncate bursts.
34 integrated silicon solution, inc. rev.b 10/22/2011 IS43R16400B read burst showing cas latency notes: do n = data out from column n burst length = 4 3 subsequent elements of data out appear in the programmed order following do n
integrated silicon solution, inc. 35 rev.b 10/22/2011 IS43R16400B consecutive read bursts notes: do n (or b) = data out from column n (or column b) burst length = 4 or 8 (if 4, the bursts are concatenated; if 8, the second burst interrupts the frst) 3 subsequent elements of data out appear in the programmed order following do n 3 (or 7) subsequent elements of data out appear in the programmed order following do b read commands shown must be to the same device
36 integrated silicon solution, inc. rev.b 10/22/2011 IS43R16400B non-consecutive read bursts notes: do n (or b) = data out from column n (or column b) burst length = 4 3 subsequent elements of data out appear in the programmed order following do n (and following do b)
integrated silicon solution, inc. 37 rev.b 10/22/2011 IS43R16400B random read bursts notes: do n, etc. = data out from column n, etc. n , etc. = the next data out following do n, etc. according to the programmed burst order burst length = 2, 4 or 8 in cases shown. if burst of 4 or 8, the burst is interrupted, reads are to active rows in any banks
38 integrated silicon solution, inc. rev.b 10/22/2011 IS43R16400B terminating a read burst notes: do n = data out from column n cases shown are bursts of 8 terminated after 4 data elements 3 subsequent elements of data out appear in the programmed order following do n
integrated silicon solution, inc. 39 rev.b 10/22/2011 IS43R16400B read to write notes: do n (or b) = data out from column n (or column b) burst length = 4 in the cases shown (applies for bursts of 8 as well; if burst length is 2, the bst command shown can be nop) 1 subsequent element of data out appears in the programmed order following do n data in elements are applied following di b in the programmed order
40 integrated silicon solution, inc. rev.b 10/22/2011 IS43R16400B read to precharge notes: do n = data out from column n cases shown are either uninterrupted bursts of 4, or interrupted bursts of 8 3 subsequent elements of data out appear in the programmed order following do n precharge may be applied at (bl/2) tck after the read command. note that precharge may not be issued before tras ns after the active command for applicable banks. the active command may be applied if trc has been met.
integrated silicon solution, inc. 41 rev.b 10/22/2011 IS43R16400B write the write command is used to initiate a burst write access to an active row, with a burst length as set in the mode register. ba0 and ba1 select the bank, and the address inputs select the starting column location. the value of a10 determines whether or not auto precharge is used. if auto precharge is selected, the row being accessed will be precharged at the end of the write burst; if auto precharge is not selected, the row will remain open for subsequent accesses. basic write timing parameters for dqs are shown in figure basic write timing parameters; they apply to all write operations. input data appearing on the data bus, is written to the memory array subject to the dm input logic level appearing coincident with the data. if a given dm signal is registered low, the corresponding data will be written to the memory; if the dm signal is registered high, the corresponding data inputs will be ignored, and a write will not be executed to that byte / column location. write command note: all command and timing diagrams are with ap = a10.
42 integrated silicon solution, inc. rev.b 10/22/2011 IS43R16400B during write bursts, the frst valid data-in element will be registered on the frst rising edge of dqs following the write command, and the subsequent data elements will be registered on successive edges of dqs. the low state of dqs between the write command and the frst rising edge is called the write preamble, and the low state on dqs following the last data-in element is called the write postamble. the time between the write command and the frst corresponding rising edge of dqs (tdqss) is specifed with a relatively wide range - from 75% to 125% of a clock cycle. the fgure below shows the two extremes of tdqss for a burst of 4. upon completion of a burst, assuming no other commands have been initiated, the dqs will remain high-z and any additional input data will be ignored. write to write data for any write burst may be concatenated with or truncated with a subsequent write command. in either case, a continuous fow of input data, can be maintained. the new write command can be issued on any positive edge of the clock following the previous write command. the frst data-in element from the new burst is applied after either the last element of a completed burst or the last desired data element of a longer burst which is being truncated. the new write command should be issued x cycles after the frst write command, where x equals the number of desired data-in element pairs. write to read data for any write burst may be followed by a subsequent read command. to follow a write without truncating the write burst, twtr should be met as shown in non-interrupting write to read. data for any write burst may be truncated by a subsequent read command as shown in figure interrupting write to read. note that the only data-in pairs that are registered prior to the twtr period are written to the internal array, and any subsequent data-in must be masked with dm. write burst (min. and max. tdqss) notes: di b = data in for column b 3 subsequent elements of data in are applied in the programmed order following di b a non--interrupted burst of 4 is shown ap is low with the write command (auto precharge disabled)
integrated silicon solution, inc. 43 rev.b 10/22/2011 IS43R16400B write to precharge: data for any write burst may be followed by a subsequent precharge command to the same bank (provided auto precharge was not activated). to follow a write without truncating the write burst, twr should be met. data for any write burst may be truncated by a subsequent precharge command. note that only data-in pairs that are registered prior to the twr period are written to the internal array, and any subsequent data-in should be masked with dm. following the precharge command, a subsequent command to the same bank cannot be issued until trp is met. write bursts notes: di b = data in for column b three elements of data are applied in the programmed order following di a noninterrupted burst of 4 is shown ap is low with the write command (autoprecharge is disabled) for a x16, udm and ldm would be required, as well as udqs and ldqs.
44 integrated silicon solution, inc. rev.b 10/22/2011 IS43R16400B non-consecutive write bursts notes: di b, etc. = data in for column b, etc. three subsequent elements of data in are applied in the programmed order following di b three subsequent elements of data in are applied in the programmed order following di n noninterrupted bursts of 4 are shown each write command may be to any bank and may be to the same or different devices
integrated silicon solution, inc. 45 rev.b 10/22/2011 IS43R16400B random write cycles notes: di b, etc. = data in for column b, etc. b, etc. = the next data in following di b, etc. according to the programmed burst order. programmed burst length = 2, 4, or 8 in cases shown. if burst of 4 or 8, the burst would be truncated. each write command may be to any bank and may be to the same or different devices.
46 integrated silicon solution, inc. rev.b 10/22/2011 IS43R16400B non-interrupting write to read notes: di b = data in for column b three subsequent elements of data in are applied in the programmed order following di b a non-interrupted burst of 4 is shown twtr is referenced from the frst positive ck edge after the last data in pair twtr = 2tck for optional cl = 1.5 (otherwise twtr = 1tck) ap is low with the write command (auto precharge is disabled) the read and write commands are to the same device but not necessarily to the same bank
integrated silicon solution, inc. 47 rev.b 10/22/2011 IS43R16400B interrupting write to read notes: di b = data in for column b an interrupted burst of 8 is shown, 4 data elements are written three subsequent elements of data in are applied in the programmed order following di b twtr is referenced from the frst positive ck edge after the last data in pair twtr = 2tck for optional cl = 1.5 (otherwise twtr = 1tck) ap is low with the write command (auto precharge is disabled) the read and write commands are to the same device but not necessarily to the same bank
48 integrated silicon solution, inc. rev.b 10/22/2011 IS43R16400B non-interrupting write to precharge notes: di b = data in for column b three subsequent elements of data in are applied in the programmed order following di b a non-interrupted burst of 4 is shown twr is referenced from the frst positive ck edge after the last data in pair ap is low with the write command (auto precharge is disabled)
integrated silicon solution, inc. 49 rev.b 10/22/2011 IS43R16400B interrupting write to precharge notes: di b = data in for column b an interrupted burst of 4 or 8 is shown, 2 data elements are written twr is referenced from the frst positive ck edge after the last desired data in pair ap is low with the write command (auto precharge is disabled) *1 = can be dont care for programmed burst length of 4 *2 = for programmed burst length of 4, dqs becomes dont care at this point
50 integrated silicon solution, inc. rev.b 10/22/2011 IS43R16400B precharge the precharge command is used to deactivate the open row in a particular bank or the open row in all banks. the bank(s) will be available for a subsequent row access a specifed time (trp) after the precharge command is issued. input a10 determines whether one or all banks are to be precharged. in case where only one bank is to be precharged, inputs ba0, ba1 select the bank. otherwise ba0, ba1 are treated as dont care. once a bank has been precharged, it is in the idle state and must be activated prior to any read or write command being issued. a precharge command will be treated as a nop if there is no open row in that bank, or if the previously open row is already in the process of precharging. auto precharge auto precharge is a feature which performs the same individual bank precharge function as described above, but without requiring an explicit command. this is accomplished by using a10 = high, to enable auto precharge in conjunction with a specifc read or write command. a precharge of the bank / row that is addressed with the read or write command is automatically performed upon completion of the read or write burst. auto precharge is non persistent in that it is either enabled or disabled for each individual read or write command. auto precharge ensures that a precharge is initiated at the earliest valid stage within a burst. the user must not issue another command to the same bank until the precharging time (trp) is completed. this is determined as if an explicit precharge command was issued at the earliest possible time, as described for each burst type in the operation section of this specifcation. burst terminate the burst terminate command is used to truncate read bursts (with auto precharge disabled). the most recently registered read command prior to the burst terminate command will be truncated. note that the burst terminate command is not bank specifc. this command should not be used to terminate write bursts. precharge command note: all command and timing diagrams are with ap = a10.
integrated silicon solution, inc. 51 rev.b 10/22/2011 IS43R16400B refresh requirements ddr sdram devices require a refresh of all rows in any 64ms. each refresh is generated in one of two ways: by an explicit auto refresh command, or by an internally timed event in self refresh mode. dividing the number of device rows into the rolling 64ms interval defnes the average refresh interval (trefi), which is a guideline to controllers for distributed refresh timing. auto refresh auto refresh command is used during normal operation of the ddr sdram. this command is non persistent, so it must be issued each time a refresh is required. the refresh addressing is generated by the internal refresh controller. the ddr sdram requires auto refresh commands at an average periodic interval of trefi. auto refresh command notes: * = dont care, if ap is high at this point; ap must be high if more than one bank is active (i.e., must precharge all active banks) pre = precharge, act = active, ra = row address, ba = bank address, ar = autorefresh nop commands are shown for ease of illustration; other valid commands may be possible after trfc. dm, dq and dqs signals are all dont care/high--z for operations shown
52 integrated silicon solution, inc. rev.b 10/22/2011 IS43R16400B self refresh the self refresh command can be used to retain data in the ddr sdram, even if the rest of the system is powered down. when in the self refresh mode, the ddr sdram retains data without external clocking. the ddr sdram device has a built-in timer to accommodate self refresh operation. the self refresh command is initiated like an auto refresh command except cke is low. input signals except cke are dont care during self refresh. the user may halt the external clock one clock after the self refresh command is registered. once the command is registered, cke must be held low to keep the device in self refresh mode. the clock is internally disabled during self refresh operation to save power. the minimum time that the device must remain in self refresh mode is trfc. the procedure for exiting self refresh requires a sequence of commands. first, the clock must be stable prior to cke going back high. once self refresh exit is registered, a delay of at least txs must be satisfed before a valid command can be issued to the device to allow for completion of any internal refresh in progress. the use of self refresh mode introduces the possibility that an internally timed refresh event can be missed when cke is raised for exit from self refresh mode. upon exit from self refresh an extra auto refresh command is recommended.
integrated silicon solution, inc. 53 rev.b 10/22/2011 IS43R16400B self refresh command notes: * = device must be in the all banks idle state prior to entering self refresh mode ** = txsnr is required before any non--read command can be applied, and txsrd (200 cycles of ck) is required before a read command can be applied.
54 integrated silicon solution, inc. rev.b 10/22/2011 IS43R16400B power-down power-down is entered when cke is registered low (no accesses can be in progress). if power-down occurs when all banks are idle, this mode is referred to as precharge power-down; if power-down occurs when there is a row active in any bank, this mode is referred to as active power-down. for maximum power savings, the user has the option of disabling the dll prior to entering power--down. in that case, the dll must be enabled after exiting power--down, and 200 clock cycles must occur before a read command can be issued. however, power--down duration is limited by the refresh requirements of the device, so in most applications, the self--refresh mode is preferred over the dll--disabled power--down mode. entering power-down deactivates the input and output buffers, excluding ck, ck and cke. in power-down mode, cke low must be maintained, and all other input signals are dont care. the minimum power-down duration is specifed by tcke. however, power-down duration is limited by the refresh requirements of the device. the power-down state is synchronously exited when cke is registered high (along with a nop or deselect command). a valid command may be applied txp after exit from power-down. power-down entry and exit notes: no column accesses are allowed to be in progress at the time power--down is entered * = if this command is a precharge all (or if the device is already in the idle state) then the power--down mode shown is precharge power down. if this command is an active (or if at least one row is already active) then the power--down mode shown is active power down.
integrated silicon solution, inc. 55 rev.b 10/22/2011 IS43R16400B input clock frequency change during precharge power down the ddr sdram input clock frequency can be changed under following condition: ddr sdram must be in precharged power down mode with cke at logic low level. after a minimum of 2 clocks after cke goes low, the clock frequency may change to any frequency between minimum and maximum operating frequency specifed for the particular speed grade. during an input clock frequency change, cke must be held low. once the input clock frequency is changed, a stable clock must be provided to dram before precharge power down mode may be exited. the dll must be reset via emrs after precharge power down exit. an additional mrs command may need to be issued to appropriately set cl etc.. after the dll relock time, the dram is ready to operate with new clock frequency. clock frequency change in precharge power down mode
56 integrated silicon solution, inc. rev.b 10/22/2011 IS43R16400B 4mx16 ordering information - vdd = 2.5v commercial range: 0c to +70c frequency speed (ns) order part no. package 250 mhz 4 IS43R16400B-4tl 66-pin tsop-ii, lead-free 200 mhz 5 IS43R16400B-5tl 66-pin tsop-ii, lead-free 166 mhz 6 IS43R16400B-6tl 66-pin tsop-ii, lead-free industrial range: -40c to +85c frequency speed (ns) order part no. package 200 mhz 5 IS43R16400B-5tli 66-pin tsop-ii, lead-free 166 mhz 6 IS43R16400B-6tli 66-pin tsop-ii, lead-free
integrated silicon solution, inc. 57 rev.b 10/22/2011 IS43R16400B note : 4. formed leads shall be planar with respect to one another within 0.1mm 3. dimension b does not include dambar protrusion/intrusion. 2. dimension d and e1 do not include mold protrusion . at the seating plane after final test. 1. controlling dimension : mm package outline 10/04/2006

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